Integral INSSD64GP25MXZ Datasheet Page 1

TECHNICAL DATASHEETIntegral Z Series PATA 2.5 Inch SpecificationVersion 1.1

10 PIO timing parameters Mode 0 ns Mode 1 ns Mode2 ns Mode 3 ns Mode 4 ns Note t0 Cycle time (min) 600 383 240 180 120 1,4 t1 Ad

11 3. The delay from the activation of FIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait unt

12 (Sustaining a Multiword DMA data burst) (Device terminating a Multiword DMA data burst)

13 (Host terminating a Multiword DMA data burst)

14 Multiword DMA timing parameters Mode 0 ns Mode 1 ns Mode2 ns Note t0 Cycle time (min) 480 150 1

15 3.3.3 Ultra DMA Data Transfer Ultra DMA data burst timing requirements

16 Ultra DMA data burst timing descriptions

17 (Initialing an Ultra DMA data-in burst) (Sustained Ultra DMA data-in burst)

18 (Device terminating an Ultra DMA data-in burst) (Host terminating an Ultra DMA data-in burst)

19 (Initialing an Ultra DMA data-out data burst) (Sustained Ultra DMA data-out burst)

2 Features:  Standard 50pin 2.5” formfactor  Standard ATA/IDE Bus Interface - 512 Bytes / Sector - ATA command set compatible - Se

20 (Host terminating an Ultra DMA data-out burst) (Device terminating an Ultra DMA data-out burst)

21 3.4 Power Management System Power Consumption: (Ta = 0 to 700C) Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 5V - 130 - mA Ic

22 4.2 Command Sets Below table summarizes the PATA 2.5” SSD command set with the paragraphs that follow describing the individual commands and ta

23 4.3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device. The parameter words in

24 Word Address Default Value Total Bytes Data Field Type Information 57-58 xxxxh 4 Current capacity in sectors (LBAs)(Word 57= LSW, Word 58= MSW)

25 5.0 Physical Dimension 5.1 2.5” PATA SSD (Top view) (Bottom view) Unit: mm

3 TABLE OF CONTENTS 1.0 BLOCK DIAGRAM ...

4 1.0 Block Diagram 1.1 Capacity Specification Density Total Bytes Cylinders Heads Sectors Total LBA 32GB 31,272,321,024 16383 16 63 61,078,75

5 31 INTRQ 32 IOIS16 33 DA1 34 -PDIAG:-CBLID 35 DA0 36 DA2 37 -CS0 38 -CS1 39 -DASP 40 GND 41 VCC 42 VCC 43 GND 44 NC 2.2 Pin Description Pi

6 IORDY(I/O channel ready) This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond

7 -CBLID(Cable assembly type identify) 37, 38 -CS0, -CS1(Chip select) I These signals are used to select the Command Block and Control Block reg

8 3.2 DC Characteristics of 5.0V I/O Cells(Host Interface) Symbol Parameter Conditions MIN TYP MAX Unit Vil Input Low Voltage -- -- 0.85 V Vih In

9 3.3 AC Characteristics 3.3.1 PIO Data Transfer