Integral INPCIE32G70MXB Datasheet download pdf (Page 6)

6

33

NC

34

GND

35

GND

36

NC

37

HA0

38

NC

39

HA1

40

GND

41

HA2

42

IORDY

43

nIOIS16

44

INTRQ

45

nPDIAG

46

nHCS0

47

3V3

48

nHCS1

49

3V3

50

GND

51

3V3

52

nDASP

2.2 Pin Description

Pin No.

Signal

I/O*

Description

22

-RESET

I

Hardware reset signal from the host

1, 3, 5, 7, 11, 13, 17,

19, 20, 16, 14, 12,

10, 8, 6, 2

HD0~HD15(Device Data)

I/O

16-bit bi-direction Data Bus. DD(7:0) are

used for 8-bit register transfers.

32

DMARQ(DMA Request)

O

For DMA data transfers. Device will

assert DMARQ when the device is ready

to transfer data to or from the host.

24

-DIOW(I/O Write)

I

This is the strobe signal used by the host

to write to the device register or Data

port

STOP(Stop UDMA Burst)

The host assert this signal during an

UDMA burst to stop the DMA burst

42

IORDY(I/O channel ready)

O

This signal is used to temporarily stop

the host register access (read or write)

when the device is not ready to respond

to a data transfer request.

DDMARDY(UDMA ready)

The device will assert this signal to

indicate that the device is ready to

receive UDMA data-out burst.

DSTROBE(UDMA data

strobe)

When UDMA mode DMA Read is active,

this signal is the data-in strobe generated

by the device.

26

CSEL(Cable select)

I

This pin is used to configure this device

1 2 3 4 5 6 7 8 9 10 11 ... 25 26

Comments to this Manuals

No comments